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The trace processor [37], for instance, proposes a hierarchical control structure that uses very aggressive control and data speculation to expose more parallel instructions to be issued in a very wide superscalar-Hke configuration. This approach appears to be very effective for improving instruction-level parallelism within the single thread of execution within a single compute node. Very long instruction word (VLIW) processors [38] also attempt to issue multiple instructions in a single cycle.

2 we review the key approaches being considered today in the area of processor architecture in light of application trends. Performance growth of microprocessors has been quite substantial, but the pace at which memory-system performance has increased has been more modest. Since the speed-gap between the processor and the memory is particularly devastating for multiprocessors, we end this section by focusing on directions of architectural improvements of memory systems for multiprocessors. 3. 1 Impact of Application Trends Considering that architectural research has been driven by the demands of numerically intensive applications, the key question is whether their machine interactions reflect those of the data intensive apphcations that dominate the market and seem to grow in importance.

The previous generation of simulation methods was too slow to make modehng of even a fraction of a second of such a system feasible. Recent advances in simulation techniques, as exemplified by the SimlCS [33] SHARED-MEMORY MULTIPROCESSING 17 and SimOS systems [34] have made it possible to get some insights into the machine interactions of these complex codes, but significant progress in evaluation methodologies is needed to help designers make architectural tradeoffs for such applications. An important goal is to be able to understand particularly how problem scaling impacts on the performance interaction.

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